Fabrication of semiconductor devices generally involves a procedure of forming thin films and layers of various materials on wafers of base semiconductor materials, and removing selected areas of such films to provide structures and circuitry. Tungsten is one of the materials commonly deposited on wafers during fabrication. Tungsten provides many advantageous features that render it especially amenable for forming electrical interconnections including plugs and interconnecting stripes. In this capacity, tungsten film is deposited into contact holes, and etched or polished to an intermediate insulating layer, leaving tungsten plugs remaining in the contact holes. Where the interconnecting stripes are desired, the deposited tungsten film is patterned with photoresist and anisotropically etched, leaving the interconnecting stripes over the insulating layer.
Chemical vapor deposition (CVD) is a well-known process for depositing the tungsten films. In a typical CVD process for forming the tungsten films, wafers are placed on supports within a sealable chamber, the chamber is sealed and evacuated, the wafers are heated, and a gas mixture is introduced into the chamber. A source gas comprising tungsten hexafluoride (WF6) is subjected to reduction by hydrogen gas, silane (SiH4) gas or a mixture of hydrogen and silane. Typically the gases flow continuously during the process. Temperature of the substrate (wafer) to be coated is one of variables that drive the chemical reaction to cause tungsten to be deposited on the substrate surface. It is important to control the temperature and the concentration of the gases in the mixture introduced in the tungsten CVD process.
According to a number of studies, while low tensile stress films are promoted by a relatively lower flow rate of WF6 and relatively higher wafer temperature, step coverage is promoted by a relatively higher flow rate of WF6 and relatively lower wafer temperature. High tensile stress of a film induces distortion of the wafer on which the film is deposited. This distortion of the wafer makes an adjustment of focus extremely difficult during a photo process to be performed after the deposition of the film. The step coverage is a measure of how well a deposited layer maintains its nominal thickness as it crosses a step. This measure is illustrated in Wolf, S., “Silicon Processing for the VLSI Era”, Vol.2, Lattice Press, Sunset Beach, Calif., (1990), p.202.
Low tensile stress films are known to be quite important for interconnecting stripe applications, but tensile stress is not as critical for plug applications. Similarly, good step coverage is desirable for plug applications, but relatively less critical for interconnecting stripe applications. Because of the different requirements for tungsten film characteristics and the dependence on process parameters as described above, the optimization of process for both plug and interconnecting stripe application was very difficult. A number of approaches to address this issue in the optimization of tungsten CVD process have been reported, including U.S. Pat. No. 5,272,112 to Johannes J. Schmitz et al. and U.S. Pat. No. 6,030,893 to Yung-Tsun Lo et al.
FIGS. 1 and 2 are a cross sectional schematic view and a scanning electron microscope (SEM) view respectively illustrating a process for forming an electrical interconnection in a semiconductor device according to a prior art disclosed in the '893 Lo et al. patent.
Referring to FIG. 1, a conductive region 3 is formed in a substrate 1. A dielectric layer 5 is then deposited on the substrate 1 and the conductive region 3. The dielectric layer 3 is etched to form a contact hole 11 exposing the conductive region. After that, the wafer is sent into a first chamber to form a lower conductive layer 7 on the dielectric layer 5 and in the contact hole 11 to contact the conductive region 3. The lower conductive layer 7 is a CVD tungsten film, which has the properties of high tensile stress and suitable step coverage. Thereafter, the wafer is sent into a second chamber to form an upper conductive layer 9 on the lower conductive layer 5. The upper conductive layer 9 is a CVD tungsten film, which has the properties of low tensile stress and moderate step coverage. The combination of the two tungsten layers is patterned with photoresist and anisotropically etched, leaving an interconnecting stripe over the dielectric layer.
However, according to the prior art, the anisotropic etching procedure is unable to entirely remove the combination of the two tungsten layers, leaving residue on the dielectric layer. The residue may cause undesired electrical connection between the interconnecting stripes. FIG. 2 shows an example of an undesired electrical connection between adjacent stripes.